The principle of a time difference amplifier (TDA) was announced in 2003. Since then, many research institutes have enthusiastically made research and development. In 2008, a team of A. A. Abide confirmed operations in circuit implementations and actual silicon, and reported applications to high-resolution time-to-digital converters (TDCs). A cascaded time difference amplifier circuit has been announced for a TDC in an ADPLL (All Digital Phase Locked Loop).
When cascading time difference amplifiers, a conventional technique wires them to shorten the wiring length. Since a wiring arrangement considering a time difference offset has not been examined, the time difference offset becomes large. Particularly, a large offset is generated in a wiring arrangement which increases the time difference offset in time difference amplifiers at respective stages (wiring arrangement has 2(n-1) combinations wherein n is the number of stages).